Renesas Electronics /R7FA6T2BD /ADC_B /ADTRGDLR2

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Interpret as ADTRGDLR2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TRGDLY40TRGDLY5

Description

A/D Conversion Start Trigger Delay Register 2

Fields

TRGDLY4

Scan Group 4 Trigger Input Delay Configuration

TRGDLY5

Scan Group 5 Trigger Input Delay Configuration

Links

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